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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) http://www.cirrus.com cs4392 24-bit, 192 khz stereo dac with volume control features complete stereo dac system: interpolation, d/a, output analog filtering 114 db dynamic range 100 db thd+n up to 192khz sample rates direct stream digital mode low clock jitter sensitivity single +5 v power supply selectable digital filters ? fast and slow roll-off volume control with soft ramp ?1dbstepsize ? zero crossing click-free transitions direct interface with 5 v to 1.8 v logic atapi mixing functions pin compatible with the cs4391 description the cs4392 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order delta-sigma digital-to-analog conversion, digital de-emphasis, vol- ume control, channel mixing and analog filtering. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture, and a high tolerance to clock jitter. the cs4392 accepts pcm data at sample rates from 4 khz to 192 khz, dsd audio data, has selectable digital filters, and consumes very little power. these features are ideal for dvd, sacd players, a/v receivers, cd and set-top box systems. the cs4392 is pin and register compatible with the cs4391, making easy performance upgrades possible. ordering information cs4392-ks -10 to 70 c 20-pin soic CS4392-KZ -10 to 70 c 20-pin tssop cdb4392 evaluation board i lrck sdata (sda/cdin) mclk amutec aouta- aoutb- serial port interpolation interpolation (control port) ? dac dac external analog filter analog filter ? mute control filter filter rst sclk volume control volume control mixer (scl/cclk) (ad0/cs ) aouta+ aoutb+ cmout reference filt+ bmutec m1 m3 m2 mode select m0 sep ?02 ds459pp2
cs4392 2 ds459pp2 table of contents 1. pin description - pcm data mode .................................................................... 5 1.1 pin description - dsd mode ..................................................................... 6 2. typical connection diagrams ........................................................................ 7 3. applications ........................................................................................................... 9 3.1 recommended power-up sequence for hardware mode ................................ 9 3.2 recommended power-up sequence and access to control port mode ............................................................................................. 9 3.3 analog output and filtering .............................................................................. 9 3.4 interpolation filter ........................................................................................... 10 3.5 system clocking ............................................................................................. 10 3.6 digital interface format .................................................................................. 11 3.7 de-emphasis .................................................................................................. 12 3.8 oversampling modes ...................................................................................... 12 3.9 using dsd mode ............................................................................................ 13 3.10 mute control ................................................................................................. 13 4. control port interface ................................................................................. 14 4.0.1 map auto increment ............................................................................. 14 4.0.2 i2c mode ............................................................................................... 14 i2c write.................................................................................................... 14 i2c read ................................................................................................... 15 4.0.3 spi mode ............................................................................................... 16 spi write.................................................................................................... 16 4.1 memory address pointer (map) ...................................................................... 16 5. register quick reference ............................................................................. 17 6. register description ........................................................................................ 18 6.1 mode control 1 - address 01h ........................................................................ 18 6.1.1 auto-mute (bit 7) ................................................................................... 18 6.1.2 digital interface formats (bits 6:4) ........................................................ 18 6.1.3 de-emphasis control (bits 3:2) ............................................................. 19 6.1.4 functional mode (bits 1:0) .................................................................... 19 6.2 volume and mixing control (address 02h) ..................................................... 20 6.2.1 channel a volume = channel b volume (bit 7) .................................... 20 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advan ce" product infor- mation describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe th at the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" witho ut warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that in formation being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, inclu ding those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, in cluding use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the prop erty of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the info rmation only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying suc h as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in thi sma- terial and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the p rc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warrant- ed to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be tr ade- marks or service marks of their respective owners.
cs4392 ds459pp2 3 6.2.2 soft ramp or zero cross enable (bits 6:5) ...........................................20 6.2.3 atapi channel mixing and muting (bits 4:0) .........................................20 6.3 channel a volume control - address 03h ......................................................22 6.4.1 mute (bit 7) ............................................................................................22 6.4.2 volume control (bits 6:0) .......................................................................22 6.5 mode control 2 - address 05h ........................................................................22 6.5.1 invert signal polarity (bits 7:6) ...............................................................22 6.5.2 control port enable (bit 5) .....................................................................23 6.5.3 power down (bit 4) ................................................................................23 6.5.4 amutec = bmutec (bit 3) ..................................................................23 6.5.5 freeze (bit 2) .........................................................................................23 6.5.6 master clock divide (bit 1) ....................................................................23 6.6 mode control 3 - address 06h ........................................................................23 6.6.1 interpolation filter select (bit 4) .............................................................23 6.6.2 soft volume ramp-up after reset (bit 3) ..............................................24 6.6.3 soft ramp-down before reset (bit 2) ....................................................24 6.7 chip id - register 07h .....................................................................................24 7. characteristics/specifications ..................................................................25 analog characteristics (cs4392-ks/kz) ..................................................25 combined interpolation & on-chip analog filter response ............................................................................................................26 switching characteristics - serial audio interface .......................32 switching specifications - dsd interface.............................................33 switching characteristics - control port interface....................34 switching characteristics - spi control port ..................................35 dc electrical characteristics .................................................................36 digital input characteristics & specifications .................................36 recommended operating specifications ..............................................37 absolute maximum ratings..........................................................................37 8. parameter definitions ......................................................................................38 9. references ............................................................................................................38 10. package dimensions ........................................................................................39 list of tables table 1. clock ratios ............................................................................................................. ....... 10 table 2. single speed (4 to 50 khz sample rates) common clock frequencies ......................... 10 table 3. double speed (50 to 100 khz sample rates) common clock frequencies................... 10 table 4. quad speed (100 to 200 khz sample rates) common clock frequencies ................... 10 table 5. digital interface format, stand-alone mode options...................................................... 11 table 5. de-emphasis select, stand-alone mode........................................................................ 12 table 6. mode selection, stand-alone mode options .................................................................. 12 table 7. direct stream digital (dsd), stand-alone mode options ............................................... 13 table 8. digital interface formats - pcm modes .......................................................................... 18 table 10. de-emphasis mode selection...................................................................................... 19 table 11. functional mode selection............................................................................................ 19 table 12. soft cross or zero cross mode selection.................................................................... 20 table 13. atapi decode ............................................................................................................ .. 21 table 14. digital volume control example settings ..................................................................... 22
cs4392 4 ds459pp2 list of figures figure 1. typical connection diagram - pcm mode....................................................................... 7 figure 2. typical connection diagram - dsd mode ....................................................................... 8 figure 3. cs4392 output filter ..................................................................................................... .. 9 figure 4. format 0, left justified up to 24-bit data....................................................................... 11 figure 5. format 1, i2s up to 24-bit data ..................................................................................... 11 figure 6. format 2, right justified 16-bit data format 3, right justified 24-bit data format 4, right justified 20-bit data. (available in control port mode only) format 5, right justified 18-bit data. (available in control port mode only)................ 11 figure 7. de-emphasis curve ....................................................................................................... 12 figure 8. control port timing, i2c mode....................................................................................... 15 figure 9. control port timing, spi mode ...................................................................................... 16 figure 10. de-emphasis curve ..................................................................................................... 1 9 figure 11. atapi block diagram .................................................................................................. 21 figure 12. single speed (fast) stopband rejection ...................................................................... 28 figure 13. single speed (fast) transition band ............................................................................ 28 figure 14. single speed (fast) transition band (detail) ................................................................ 28 figure 15. single speed (fast) passband ripple .......................................................................... 28 figure 16. single speed (slow) stopband rejection..................................................................... 28 figure 17. single speed (slow) transition band ........................................................................... 28 figure 18. single speed (slow) transition band (detail) ............................................................... 29 figure 19. single speed (slow) passband ripple ......................................................................... 29 figure 20. double speed (fast) stopband rejection..................................................................... 29 figure 21. double speed (fast) transition band ........................................................................... 29 figure 22. double speed (fast) transition band (detail) ............................................................... 29 figure 23. double speed (fast) passband ripple ......................................................................... 29 figure 24. double speed (slow) stopband rejection ................................................................... 30 figure 25. double speed (slow) transition band.......................................................................... 30 figure 26. double speed (slow) transition band (detail).............................................................. 30 figure 27. double speed (slow) passband ripple........................................................................ 30 figure 28. quad speed (fast) stopband rejection ....................................................................... 30 figure 29. quad speed (fast) transition band.............................................................................. 30 figure 30. quad speed (fast) transition band (detail).................................................................. 31 figure 31. quad speed (fast) passband ripple............................................................................ 31 figure 32. quad speed (slow) stopband rejection ...................................................................... 31 figure 33. quad speed (slow) transition band ............................................................................ 31 figure 34. quad speed (slow) transition band (detail) ................................................................ 31 figure 35. quad speed (slow) passband ripple .......................................................................... 31 figure 36. serial mode input timing ............................................................................................. 32 figure 37. direct stream digital - serial audio input timing......................................................... 33 figure 38. i2c mode control port timing...................................................................................... 34 figure 39. spi control port timing ............................................................................................... 35
cs4392 ds459pp2 5 1. pin description - pcm data mode rst 1 reset ( input ) - powers down device and resets all internal registers to their default settings. vl 2 logic power ( input ) - positive power for the digital input/output. sdata 3 serial audio data ( input ) - input for two?s complement serial audio data. sclk 4 serial clock ( input / output ) - serial clock for the serial audio interface. lrck 5 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. filt+ 11 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. cmout 12 common mode voltage ( output ) - filter connection for internal quiescent voltage. amutec bmutec 20 13 mute control ( output ) - the mute control pin goes high during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. aoutb- aoutb+ aouta+ aouta 14 15 18 19 differential analog output ( outputs ) - the full scale differential analog output level is specified in the analog characteristics specification table. agnd 16 ground ( input ) va 17 analog power ( input ) - positive power for the analog section. control port mode definitions m3 7 mode selection ( input ) - this pins should be tied to gnd level during control port mode. scl/cclk 8 serial control port clock ( input ) - serial clock for the serial control port. sda/cdin 9 serial control data ( input/output ) - sda is a data i/o line in i 2 c mode. cdin is the input data line for the control port interface in spi mode. ad0/cs 10 address bit 0 (i 2 c) / control port chip select (spi) ( input/output )-ad0isachipaddresspinini 2 c mode; cs is the chip select signal for spi format. stand-alone mode definitions m3 m2 m1 m0 7 8 9 10 mode selection ( input ) - determines the operational mode of the device. rst amutec vl aouta- sdata aouta+ sclk va lrck agnd mclk aoutb+ m3 aoutb- ( scl/cclk) m2 bmutec ( sda/cdin) m1 cmout ( ad0/cs )m0 filt+ 1 2 3 4 20 19 18 17 5 6 7 8 16 15 14 13 9 10 12 11
cs4392 6 ds459pp2 1.1 pin description - dsd mode dsd_a dsd_b 3 4 dsd data ( input ) - input for direct stream digital serial audio data. dsd_mode 5 dsd mode (input) - in stand alone mode, this pin must be set to a logic ?1? for operation of dsd mode. dsd_sclk 7 dsd serial clock ( input / output ) - serial clock for the direct stream digital audio interface. rst amutec vl aouta- dsd_a aouta+ dsd_b va dsd_mode agnd mclk aoutb+ dsd_sclk aoutb- (scl/cclk) m2 bmutec (sda/cdin) m1 cmout ( ad0/cs )m0 filt+ 1 2 3 4 20 19 18 17 5 6 7 8 16 15 14 13 9 10 12 11
cs4392 ds459pp2 7 2. typical connection diagrams sclk audio data processor * external clock mclk agnd aoutb+ cs4392 sdata va aoutb- +5v analog mode select m1 (sda/cdin ) m0 (ad0/cs) aouta- aouta+ analog conditioning & mute analog conditioning & mute 17 19 18 14 15 16 1 3 4 5 8 9 10 m2 (scl/cclk) lrck 1.0 f + rst 6 m3 7 12 1.0 f 0.1 f 10 f 11 filt+ 0.1 f + + cmout bmutec 13 amutec 20 (control port) * 2 vl logic power +5v to 1.8v 0.1 f figure 1. typical connection diagram - pcm mode * a high logic level for all digital inputs should not exceed vl.
cs4392 8 ds459pp2 dsd_b audio data processor * external clock mclk agnd aoutb+ cs4392 dsd_a va aoutb- +5v analog mode select m1 (sda/ cdin) m0 (ad0/cs) aouta- aouta+ vl analog conditioning & mute analog conditioning & mute 17 19 18 14 15 16 1 2 3 4 7 8 9 10 m2 (scl/cclk) dsd_clk 1.0 f + rst 6 12 1.0 f 0.1f 10f 11 filt+ 0.1 f + + cmout bmutec 13 amutec 20 (control port) 5 dsd_mode logic power +5v to 1.8v 0.1 f figure 2. typical connection diagram - dsd mode * a high logic level for all digital inputs should not exceed vl.
cs4392 ds459pp2 9 3. applications 3.1 recommended power-up sequence for hardware mode 1) hold rst low until the power supplies, master, and left/right clocks are stable. 2) bring rst high. after 10ms the device will begin normal operation. 3.2 recommended power-up sequence and access to control port mode 1) hold rst low until the power supply, master, and left/right clocks are stable. in this state, the control port is reset to its default settings and filt+ will remain low. 2) bring rst high. the device will remain in a low power state with filt+ low and the control port is accessible. 3) write 30h to register 05h within 10 ms cycles following the release of rst . if after 10ms the control port has not been initiated with this command, the device will enter stand-alone mode. the cpen bit, however, may be written at any time after 10ms. it is recommended to write cpen before 10ms in or- der to reduce the possibility of any extraneous click or pop noise from occurring. 4) the desired register settings can be loaded while keeping the pdn bit set to 1. 5) set the pdn bit to 0. this will initiate the power-up sequence which requires approximately 10 s. 3.3 analog output and filtering the application note ?design notes for a 2-pole filter with differential input? discusses the second-order butterworth filter and differential to single-ended converter as seen in figure 3. an alternate configuration can be seen on the cdb4392. this alternate filter configuration accounts for the differing ac loads on the + and - differential output pins which are normally present in a circuit like figure 3. it also shows an ac coupling configuration which reduces the number of required ac coupling capacitors to 2 caps per chan- nel. the circuit in figure 3 may also be dc coupled, however the filter on the cdb4392 must be ac coupled. the cs4392 is a linear phase design and does not include phase or amplitude compensation for an external filter. therefore, the dac system phase and amplitude response will be dependent on the external analog circuitry. 3.01k 1.58k 3.01k 10 uf 560 1.58k 10 uf 3.32k + - 3 2 1 r17 3.32k 10 uf 680 pf c10 680 pf 2700 pf 2700 pf 47k aout - aout + analog_out figure 3. cs4392 output filter
cs4392 10 ds459pp2 3.4 interpolation filter to accommodate the increasingly complex requirements of digital audio systems, the cs4392 incorpo- rates selectable interpolation filters for each mode of operation. a fast and a slow roll-off filter is available in each of single, double, and quad speed modes. these filters have been designed to accommodate a variety of musical tastes and styles. bit 5 of the mode control 3 register (06h) is used to select which filter is used. filter specifications can be found in section 8, and filter response plots can be found in figures 12 to 35. in stand-alone mode, only the fast roll-off filter is available. 3.5 system clocking the required mclk to lrck and suggested sclk to lrck ratios are outlined in table 1. mclk can be at any phase in regards to lrck and sclk. sclk, lrck and sdata must meet the phase and timing relationships outlined in section 7. some common mclk frequencies have been outlined in tables 2 to 4. *note:these clocking ratios are only available in control port mode when the mclk divide bit is enabled. mclk/lrck sclk/lrck lrck single speed 256, 384, 512, 768, 1024* 32, 48, 64, 96, 128 fs double speed 128, 192, 256, 384, 512* 32, 48, 64 fs quad speed 64 32 (16 bits only) fs 96 32, 48 fs 128, 256* 32, 64 fs 192 32, 48, 64, 96 fs table 1. clock ratios sample rate (khz) mclk (mhz) see note 256x 384x 512x 768x 1024x* 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 2. single speed (4 to 50 khz sample rates) common clock frequencies sample rate (khz) mclk (mhz) see note 128x 192x 256x 384x 512x* 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. double speed (50 to 100 khz sample rates) common clock frequencies sample rate (khz) mclk (mhz) see note 64x 96x 128x 192x 256x* 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 4. quad speed (100 to 200 khz sample rates) common clock frequencies
cs4392 ds459pp2 11 3.6 digital interface format the device will accept audio samples in several digital interface formats as illustrated in tables 5 and 8. the desired format is selected via the m0 and m1 pins for stand alone mode, and through the dif2:0 bits in the control port. for an illustration of the required relationship between the left/right clock, serial clock and serial audio data, see figures 4-6. m1 m0 description format figure 00 left justified, up to 24-bit data 04 01 i 2 s, up to 24-bit data 15 10 right justified, 16-bit data 26 11 right justified, 24-bit data 36 table 5. digital interface format, stand-alone mode options figure 4. format 0, left justified up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 5. format 1, i 2 s up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 lrck sclk left channel sdata +5 +4 +3 +2 +1 lsb msb -1 -2 -3 -4 -5 32 clocks right channel lsb +5 +4 +3 +2 +1 lsb msb -1 -2 -3 -4 -5 +6 -6 +6 -6 figure 6. format 2, right justified 16-bit data format 3, right justified 24-bit data format 4, right justified 20-bit data. (available in control port mode only) format 5, right justified 18-bit data. (available in control port mode only)
cs4392 12 ds459pp2 3.7 de-emphasis the device includes on-chip digital de-emphasis. figure 7 shows the de-emphasis curve for f s equal to 44.1 khz. the frequency response of the de-emphasis curve will scale proportionally with changes in sam- ple rate, f s . please see table 5 for the desired de-emphasis control for stand-alone mode and table 10 for control port mode. the de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. de-emphasis is only available in single speed mode. 3.8 oversampling modes the cs4392 operates in one of three oversampling modes based on the input sample rate. mode selection is determined by the m3 and m2 pins in stand-alone mode or the fm bits in control port mode. single- speed mode supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode supports input sample rates up to 200 khz and uses an oversampling ratio of 32x m3 m2 description 00 single-speed without de-emphasis (4 to 50 khz sample rates) 01 single-speed with 44.1khz de-emphasis 10 double-speed (50 to 100 khz sample rates) 11 quad-speed (100 to 200 khz sample rates) table 6. mode selection, stand-alone mode options gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 7. de-emphasis curve m2 (dem) description figure 0 no de-emphasis 1 de-emphasis enabled 7 table 5. de-emphasis select, stand-alone mode
cs4392 ds459pp2 13 3.9 using dsd mode in stand-alone mode, dsd operation is selected by holding dsd_en(lrck) high and applying the dsd data and clocks to the appropriate pins. the m2:0 pins set the expected dsd rate and mclk ratio. in control-port mode the fm bits set the device into dsd mode (dsd_en pin is not required to be held high). the dif register then controls the expected dsd rate and mclk ratio. 3.10 mute control the mute control pins go high during power-up initialization, reset, or if the master clock to left right clock ratio is incorrect. these pins will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. a single sample of non-zero data on either channel will cause the mute control pins to go low. these pins are intended to be used as control for an external mute circuit in order to add off-chip mute capability. use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system de- signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir- cuit. see the cdb4392 data sheet for a suggested mute circuit. dsd_mode m2 m1 m0 description 1000 64x oversampled dsd data with a 4x mclk to dsd data rate 1001 64x oversampled dsd data with a 6x mclk to dsd data rate 1010 64x oversampled dsd data with a 8x mclk to dsd data rate 1011 64x oversampled dsd data with a 12x mclk to dsd data rate 1100 128x oversampled dsd data with a 2x mclk to dsd data rate 1101 128x oversampled dsd data with a 3x mclk to dsd data rate 1110 128x oversampled dsd data with a 4x mclk to dsd data rate 1111 128x oversampled dsd data with a 6x mclk to dsd data rate table 7. direct stream digital (dsd), stand-alone mode options
cs4392 14 ds459pp2 4. control port interface the control port is used to load all the internal register settings (see section 6). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i 2 c or spi. notes: mclk must be applied during all i 2 c communication. 4.0.1 map auto increment the device has map (memory address pointer) auto increment capability enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i 2 c writes or reads, and spi writes. if incr is set to 1, map will auto increment after each byte is written, allowing block reads or writes of successive registers. 4.0.2 i 2 c mode in the i 2 c mode, data is clocked into and out of the bi-directional serial control data line, sda, by the serial control port clock, scl (see figure 8 for the clock to data relationship). there is no cs pin. pin ad0 enables the user to alter the chip address (001000[ad0][r/w ]) and should be tied to vl or agnd as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 4.0.2a i 2 cwrite to write to the device, follow the procedure below while adhering to the control port switching specifications in section 7. 1) initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 0. the eighth bit of the address byte is the r/w bit. 2) wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the register to be written. 3) wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4) if the incr bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c writes to other registers are desired, it is nec- essary to initiate a repeated start condition and follow the procedure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus.
cs4392 ds459pp2 15 4.0.2b i 2 cread to read from the device, follow the procedure below while adhering to the control port switching specifications . 1) initiate a start condition to the i 2 c bus followed by the address byte. the upper 6 bits must be 001000. the seventh bit must match the setting of the ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2) after transmitting an acknowledge (ack), the device will then transmit the contents of the register pointed to by the map. the map register will contain the address of the last register written to the map, or the default address (see section 4.1) if an i 2 c read is the first operation performed on the device. 3) once the device has transmitted the contents of the register pointed to by the map, issue an ack. 4) if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. continue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c reads from other registers are desired, it is nec- essary to initiate a stop condition and follow the procedure detailed from steps 1 and 2 from the i 2 c write instructions followed by step 1 of the i 2 c read section. if no further reads from other registers are desired, initiate a stop condition to the bus. sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. control port timing, i 2 cmode
cs4392 16 ds459pp2 4.0.3 spi mode in spi mode, data is clocked into the serial control data line, cdin, by the serial control port clock, cclk (see figure 9 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 4.0.3a spi write to write to the device, follow the procedure below while adhering to the control port switching specifications in section 7. 1) bring cs low. 2) the address byte on the cdin pin must then be 00100000. 3) write to the memory address pointer, map. this byte points to the register to be written. 4) write the desired data to the register pointed to by the map. 5) if the incr bit (see section 4.0.1) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6) if the incr bit is set to 0 and further spi writes to other registers are desired, it is nec- essary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are desired, bring cs high. 4.1 memory address pointer (map) map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 9. control port timing, spi mode 4.1.1 incr (auto map increment enable) default = ? 0 ? 0 - disabled, the map will stay constant for successive writes 1 - enabled, the map will auto increment after each byte is written, allowing block reads or writes of successive registers 4.1.2 map3-0 (memory address pointer) default = ? 0000 ? 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
cs4392 ds459pp2 17 5. register quick reference addr function 7 6 5 4 3 2 1 0 01h mode control 1 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 1000 0 0 00 02h volume and mixing control a=b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 0100 1 0 01 03h channel a volume control mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 0000 0 0 00 04h channel b volume control mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 0000 0 0 00 05h mode control 2 invert_a invert_b cpen pdn mutec a = b freeze mclkdiv2 reserved 0001 0 0 00 06h mode control 3 reserved reserved reserved filt_sel rmp_up rmp_dn reserved reserved 0000 0 0 00 07h chip id part3 part2 part1 part0 rev3 rev2 rev1 rev0 1000 - - - -
cs4392 18 ds459pp2 6. register description ** all registers are read/write in two-wire mode and write only in spi mode, unless otherwise noted** 6.1 mode control 1 - address 01h 6.1.1 auto-mute (bit 7) function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static data will release the mute. detection and muting is done independently for each channel. (however, auto-mute detection and muting can be- come dependent on either channel if the mute a = b function is enabled.) the common mode on the output will be retained and the mute control pin for that channel will go active during the mute period. the muting function is effected, similar to volume control changes, by the soft and zero cross bits in the volume and mixing control register. 6.1.2 digital interface formats (bits 6:4) function: pcm mode - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in table 8 and figures 4-6. 76543210 amute dif2 dif1 dif0 dem1 dem0 fm1 fm0 dif2 dif1 difo description format figure 0 0 0 left justified, up to 24-bit data (default) 0 4 001 i 2 s, up to 24-bit data 15 0 1 0 right justified, 16-bit data 2 6 0 1 1 right justified, 24-bit data 3 6 1 0 0 right justified, 20-bit data 4 6 1 0 1 right justified, 18-bit data 5 6 110 reserved 111 reserved table 8. digital interface formats - pcm modes
cs4392 ds459pp2 19 dsd mode - the relationship between the oversampling ratio of the dsd audio data and the required master clock to dsd data rate is defined by the digital interface format pins. note that the functional mode registers must be set to dsd mode. see 9 for register options. 6.1.3 de-emphasis control (bits 3:2) function: implementation of the standard 15 s/50 s digital de-emphasis filter response, figure 7, requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. note: de-emphasis is available only in single-speed mode. see 10 below. 6.1.4 functional mode (bits 1:0) function: selects the required range of input sample rates or dsd mode. see table 11. dif2 dif1 difo description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate (default) 0 0 1 64x oversampled dsd data with a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data with a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 9. digital interface formats - dsd mode dem1 demo description 0 0 disabled (default) 0 1 44.1 khz de-emphasis 1 0 48 khz de-emphasis 1 1 32 khz de-emphasis table 10. de-emphasis mode selection gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 10. de-emphasis curve fm1 fm0 mode 0 0 single-speed mode: 4 to 50 khz sample rates (default) 0 1 double-speed mode: 50 to 100 khz sample rates 1 0 quad-speed mode: 100 to 200 khz sample rates 1 1 direct stream digital mode table 11. functional mode selection
cs4392 20 ds459pp2 6.2 volume and mixing control (address 02h) 6.2.1 channel a volume = channel b volume (bit 7) function: the aouta and aoutb volume levels are independently controlled by the a and the b channel vol- ume control bytes when this function is disabled. the volume on both aouta and aoutb are de- termined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 6.2.2 soft ramp or zero cross enable (bits 6:5) function: soft ramp enable soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1db per 8 left/right clock periods. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp and zero cross enable soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 12 6.2.3 atapi channel mixing and muting (bits 4:0) function: the cs4392 implements the channel mixing functions of the atapi cd-rom specification. see table 13 on page 21 76543210 a = b soft zero cross atapi4 atapi3 atapi2 atapi1 atapi0 soft zero mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled (default) 1 1 soft ramp and zero cross enabled table 12. soft cross or zero cross mode selection
cs4392 ds459pp2 21 atapi4 atapi3 atapi2 atapi1 atapi0 aouta aoutb 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 01111 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(bl+ar)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(al+br)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 11111 [(al+br)/2] [(al+br)/2] table 13. atapi decode ? a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 11. atapi block diagram
cs4392 22 ds459pp2 6.3 channel a volume control - address 03h see 4.4 channel b volume control - address 04h 6.4 channel b volume control - address 04h 6.4.1 mute (bit 7) function: the digital-to-analog converter output will mute when enabled. the common mode voltage on the output will be retained. the muting function is effected, similiar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. the mutec pin for that channel will go active during the mute period if the mute function is enabled. both the amutec and bmutec will go active if either mute register is enabled and the mutec a = b bit (register 5) is enabled. 6.4.2 volume control (bits 6:0) function: the digital volume control allows the user to attenuate the signal in 1 db increments from 0 to -127 db. volume settings are decoded as shown in table 14. the volume changes are implemented as dictated by the soft and zero cross bits in the volume and mixing control register (see section 6.2.2). 6.5 mode control 2 - address 05h 6.5.1 invert signal polarity (bits 7:6) function: when set to 1, this bit inverts the signal polarity for the appropriate channel. this is useful if a board layout error has occurred, or an other situations where a 180 degree phase shift is desirable. default is 0. 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db table 14. digital volume control example settings 76543210 invert_a invert_b cpen pdn mutec a = b freeze mclkdiv2 reserved
cs4392 ds459pp2 23 6.5.2 control port enable (bit 5) function: this bit defaults to 0, allowing the device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the registers and the pin definitions will conform to control port mode. to accomplish a clean power- up, the user should write 30h to register 5 within 10 ms following the release of reset. 6.5.3 power down (bit 4) function: the device will enter a low-power state whenever this function is activated (set to 1). the power-down bit defaults to ? enabled ? (1) on power-up and must be disabled before normal operation will begin. the contents of the control registers are retained when the device is in power-down. 6.5.4 amutec = bmutec (bit 3) function: when this function is enabled, the individual controls for amutec and bmutec are internally con- nected through a and gate prior to the output pins. therefore, the external amutec and bmutec pins will go active only when the requirements for both amutec and bmutec are valid. 6.5.5 freeze (bit 2) function: this function allows modifications to the control port registers without the changes taking effect until freeze is disabled. to make multiple changes in the control port registers take effect simultaneously, set the freeze bit, make all register changes, then disable the freeze bit. 6.5.6 master clock divide (bit 1) function: this function allows the user to select an internal divide by 2 of the master clock. this selection is required to access the higher master clock rates as shown in tables 2 through 4 on page 10. 6.6 mode control 3 - address 06h 6.6.1 interpolation filter select (bit 4) function: this function allows the user to select whether the interpolation filter has a fast (set to 0 - default) or slow (set to 1) roll off. the - 3db corner is approximately the same for both filters, but the slope of the roll of is greater for the ? fast ? roll off filter. b7 b6 b5 b4 b3 b2 b1 b0 reserved reserved reserved filt_sel rmp_up rmp_dn reserved reserved
cs4392 24 ds459pp2 6.6.2 soft volume ramp-up after reset (bit 3) function: this function allows the user to control whether a soft ramp up in volume is applied when reset is re- leased either by the reset pin or internal to the chip. the modes are as follows: 0 - an instantaneous change is made from max attenuation to the control port volume setting on re- lease of reset (default setting). 1 - volume is ramped up using the soft-ramp settings in bits 6:5 of register 02h (see 6.2.2) from max attenuation to the control port volume setting on release of reset. 6.6.3 soft ramp-down before reset (bit 2) function: this function allows the user to control if a soft ramp-down in volume is applied before a known reset condition. the modes are as follows: 0 - an instantaneous change is made from the control port volume setting to max attenuation when chip resets (default setting). 1 - volume is ramped down using the soft-ramp settings in bits 6:5 of register 02h (see 6.2.2) from the control port volume setting to max attenuation when chip resets. 6.7 chip id - register 07h function: this register is read-only. bits 7 through 4 are the part number id which is 1000b (8h) and the re- maining bits (3 through 0) are for the chip revision. b7 b6 b5 b4 b3 b2 b1 b0 part3 part2 part1 part0 rev3 rev2 rev1 rev0
cs4392 ds459pp2 25 7. characteristics/specifications analog characteristics (cs4392-ks/kz) ((test conditions (unless otherwise speci- fied): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth is 10 hz to 20 khz; test load r l =3k ? ,c l = 10 pf. typical performance characteristics are derived from measurements taken at t a =25 c, vl = va = 5.0v. min/max performance characteristics are guaranteed over the specified operating temperature and voltages.) notes: 1. one-half lsb of triangular pdf dither is added to data. 2. v fs is tested under load r l but does not include attenuation due to z out parameter va = 5.0v symbol min typ max unit dynamic performance for all speed modes and dsd dynamic range (note 1) unweighted a-weighted 105 108 111 114 - - db db total harmonic distortion + noise (note 1) 0db -20 db -60 db thd+n - - - -100 -91 -51 -94 - -45 db db db idle channel noise / signal-to-noise ratio - 114 - db interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/ c analog output characteristics and specifications full scale differential output voltage v fs 0.95xva 0.99xva 1.05xva vpp output resistance (note 2) z out - 100 - ? minimum ac-load resistance r l -3-k ? maximum load capacitance c l - 100 - pf
cs4392 26 ds459pp2 combined interpolation & on-chip analog filter response (the filter characteristics and the x-axis of the response plots have been normalized to the sample rate (fs) and can be referenced to the desired sample rate by multiplying the given characteristic by fs.) parameter fast roll-off unit min typ max single-speed mode - (4 khz to 50 khz sample rates) passband to -0.01 db corner to -3 db corner 0 0 - - 0.454 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 4) 90 - - db group delay - 12/fs - s passband group delay deviation 0 - 20 khz - - 0.41/fs s de-emphasis error (relative to 1khz) fs = 32 khz (note 5) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double-speed mode - (50 khz to 100 khz sample rates) passband to -0.01 db corner to -3 db corner 0 0 - - 0.430 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband 0.583 - - fs stopband attenuation (note 4) 80 - - db group delay - 4.6/fs - s passband group delay deviation 0 - 20 khz - - 0.03/fs s quad speed mode - (100 khz to 200 khz) passband to -0.01 db corner to -3 db corner 0 0 - - 0.105 0.490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband 0.635 - - fs stopband attenuation (note 4) 90 - - db group delay - 4.7/fs - s passband group delay deviation 0 - 20 khz - - 0.01/fs s dsd mode passband to -0.1 db corner to -3 db corner 0 0 - - 20 120 khz khz frequency response 10 hz to 20 khz -.01 - 0.1 db
cs4392 ds459pp2 27 combined interpolation & on-chip analog filter response (cont.) notes: 3. slow roll-off interpolation filter is only available in control port mode. 4. for single and double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 5. de-emphasis is only available in single speed mode; the 44.1khz de-emphasis filter is the only filter available in stand-alone mode. parameter slow roll-off (note 3) unit min typ max single-speed mode - (4 khz to 50 khz sample rates) passband to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.583 - - fs stopband attenuation (note 4) 64 - - db group delay - 6.5/fs - s passband group delay deviation 0 - 20 khz - 0.14/fs s de-emphasis error (relative to 1khz) fs = 32 khz (note 5) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double-speed mode - (50 khz to 100 khz sample rates) passband to -0.01 db corner to -3 db corner 0 0 - - 0.296 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband 0.792 - - fs stopband attenuation (note 4) 70 - - db group delay - 3.9/fs - s passband group delay deviation 0 - 20 khz - 0.01/fs s quad speed mode - (100 khz to 200 khz) passband to -0.01 db corner to -3 db corner 0 0 - - 0.104 0.481 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband 0.868 - - fs stopband attenuation (note 4) 75 - - db group delay - 4.2/fs - s passband group delay deviation 0 - 20 khz - 0.01/fs s dsd mode passband to -0.1 db corner to -3 db corner 0 0 - - 20 120 khz khz frequency response 10 hz to 20 khz -.01 - 0.1 db
cs4392 28 ds459pp2 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 12. single speed (fast) stopband rejection figure 13. single speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 14. single speed (fast) transition band (detail) figure 15. single speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 16. single speed (slow) stopband rejection figure 17. single speed (slow) transition band
cs4392 ds459pp2 29 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 18. single speed (slow) transition band (detail) figure 19. single speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 20. double speed (fast) stopband rejection figure 21. double speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 22. double speed (fast) transition band (detail) figure 23. double speed (fast) passband ripple
cs4392 30 ds459pp2 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 24. double speed (slow) stopband rejection figure 25. double speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 26. double speed (slow) transition band (detail) figure 27. double speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 28. quad speed (fast) stopband rejection figure 29. quad speed (fast) transition band
cs4392 ds459pp2 31 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 30. quad speed (fast) transition band (detail) figure 31. quad speed (fast) passband ripple 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 32. quad speed (slow) stopband rejection figure 33. quad speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 34. quad speed (slow) transition band (detail) figure 35. quad speed (slow) passband ripple
cs4392 32 ds459pp2 switching characteristics - serial audio interface (inputs: logic 0 = 0 v, logic 1 = vl) . parameters symbol min typ max units input sample rate fs 4 - 200 khz lrck duty cycle 45 50 55 % mclkdutycycle 405060 % sclk frequency single speed mode double speed mode quad speed mode (mclkdiv=0) quad speed mode (mclkdiv=1) - - - - - - - - 128 lrck 64 lrck mclk/2 mclk/4 hz hz hz hz sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns slrs t slrd t sdlrs t sdh t sdata sclk lrck figure 36. serial mode input timing
cs4392 ds459pp2 33 switching specifications - dsd interface (logic 0 = agnd; logic 1 = vl) parameter symbol min max unit mclk duty cycle 40 60 % dsd_sclk pulse width low t sclkl 20 - ns dsd_sclk pulse width high t sclkh 20 - ns dsd_sclk period t sclkw 20 -ns dsd_l or dsd_r valid to dsd_sclk rising setup time t sdlrs 20 - ns dsd_sclk rising to dsd_l or dsd_r hold time t sdh 20 - ns sclkh t sclkl t dsd_l, dsd_r dsd_sclk sdlrs t sdh t figure 37. direct stream digital - serial audio input timing
cs4392 34 ds459pp2 switching characteristics - control port interface (inputs: logic 0 = agnd, logic 1 = vl) notes: 6. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c mode scl clock frequency f scl -100khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 6) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of both sda and scl lines t r -1s fall time of both sda and scl lines t f - 300 ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop s tart start stop repeated sda scl t irs rst figure 38. i 2 c mode control port timing
cs4392 ds459pp2 35 switching characteristics - spi control port (inputs: logic 0 = agnd, logic 1 = vl) notes: 7. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 8. data must be held for sufficient time to bridge the transition time of cclk. 9. for f sck <1mhz parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 7) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 82 - ns cclk high time t sch 82 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 8) t dh 15 - ns rise time of cclk and cdin (note 9) t r2 - 100 ns fall time of cclk and cdin (note 9) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 39. spi control port timing
cs4392 36 ds459pp2 dc electrical characteristics (agnd = 0v; all voltages with respect to agnd.) notes: 10. normal operation is defined as rst = hi with a 997 hz, 0dbfs input sampled at f s = 48khz, and open outputs, unless otherwise stated. 11. power-down mode is defined as rst = lo with all clocks and data lines held static. 12. valid with the recommended capacitor values on filt+ and vq as shown in figures 1 and 2. digital input characteristics & specifications (agnd = 0v; all voltages with respect to agnd.) thermal characteristics and specifications parameter symbol min typ max units normal operation (note 10) power supply current all supplies=5.0v i a +i l -2630ma power dissipation - 130 150 mw power-down mode (note 11) power supply current all supplies=5.0v i a +i l -300- a power dissipation - 1.5 - mw all modes of operation power supply rejection ratio (note 12) (1 khz) (60 hz) psrr - - 60 40 - - db db common mode voltage output impedance maximum allowable dc current source/sink cmout - - - 0.48 va 250 0.001 - - - v k ? ma filt+ nominal voltage output impedance maximum allowable dc current source/sink - - - va 250 0.001 - - - v k ? ma mutec low-level output voltage - 0 - v mutec high-level output voltage - va - v maximum mutec drive current - 3 - ma parameters symbol min typ max units input leakage current i in --10 a input capacitance - 8 - pf high-level input voltage v ih 70% - - vl low-level input voltage v il - 20% vl parameters symbol min typ max units package thermal resistance cs4392-ks CS4392-KZ ja ja - - 68 72 - - c/watt c/watt ambient operating temperature (power applied) t a -10 - +70 c
cs4392 ds459pp2 37 recommended operating specifications (agnd = 0v; all voltages with respect to agnd.) absolute maximum ratings (agnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply va vl 4.75 1.8 5.0 - 5.25 va v v parameters symbol min max units dc power supply va vl -0.3 -0.3 6.0 va v v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs4392 38 ds459pp2 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/ c. 9. references 1. cdb4392 evaluation board datasheet 2. ? the i 2 c-bus specification: version 2.1 ? philips semiconductors, january 2000. http://www.semiconductors.philips.com
cs4392 ds459pp2 39 10. package dimensions notes: 1. ? d ? and ? e1 ? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ? b ? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ? b ? dimension at maximum material condition. dambar intrusion shall not reduce dimension ? b ? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters not e dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs4392 40 ds459pp2 package dimensions (cont.). inches millimeters dim min nom max min nom max a 0.093 0.098 0.104 2.35 2.50 2.65 a1 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.43 0.51 c 0.009 0.011 0.013 0.23 0.28 0.32 d 0.496 0.504 0.512 12.60 12.80 13.00 e 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.394 0.407 0.419 10.00 10.34 10.65 l 0.016 0.025 0.050 0.40 0.64 1.27 0 4 8 0 4 8 jedec #: ms-013 controlling dimension is millimeters 20l soic (300 mil body) package drawing d h e b a1 a c l seating plane e 1
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